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ISMVL
2010
IEEE
164views Hardware» more  ISMVL 2010»
13 years 10 months ago
On the Number of Products to Represent Interval Functions by SOPs with Four-Valued Variables
Abstract—Let A and B be integers such that A ≤ B. An nvariable interval function is a mapping IN[n : A, B] : {0, 1}n → {0, 1}, where IN[n : A, B](X) = 1 iff A ≤ X ≤ B. Su...
Tsutomu Sasao
ISMVL
2010
IEEE
188views Hardware» more  ISMVL 2010»
13 years 10 months ago
MDGs Reduction Technique Based on the HOL Theorem Prover
—Multiway Decision Graphs (MDGs) subsume Binary Decision Diagrams (BDDs) and extend them by a first-order formulae suitable for model checking of data path circuits. In this pap...
Sa'ed Abed, Otmane Aït Mohamed
ISMVL
2010
IEEE
156views Hardware» more  ISMVL 2010»
13 years 10 months ago
Floating-Point Numeric Function Generators Based on Piecewise-Split EVMDDs
This paper proposes a new architecture for memorybased floating-point numeric function generators (NFGs). The design method uses piecewise-split edge-valued multivalued decision ...
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
ISMVL
2010
IEEE
158views Hardware» more  ISMVL 2010»
13 years 9 months ago
An Evolutionary Algorithm for Optimization of Pseudo Kronecker Expressions
—Using EXOR gates in logic synthesis often results in smaller circuit realizations. While in AND/OR synthesis the problem definition is clear, in AND/EXOR synthesis several clas...
Alexander Finder, Rolf Drechsler
ISMVL
2010
IEEE
191views Hardware» more  ISMVL 2010»
13 years 10 months ago
Toffoli Gate Implementation Using the Billiard Ball Model
— In this paper we review the Billiard Ball Model (BBM) introduced by Toffoli and Fredkin. The analysis of a previous approach to design reversible networks based on BBM it shown...
Hadi Hosseini, Gerhard W. Dueck