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ISPD
1997
ACM
142views Hardware» more  ISPD 1997»
13 years 9 months ago
Minimization of chip size and power consumption of high-speed VLSI buffers
In this paper, we study optimal bu er design in high-performance VLSI systems. Speci cally, we design a bu er for a given load such that chip area and power dissipation are minima...
D. Zhou, X. Y. Liu
ISPD
1997
ACM
103views Hardware» more  ISPD 1997»
13 years 9 months ago
On two-step routing for FPGAS
We present results which show that a separate global and detailed routing strategy can be competitive with a combined routing process. Under restricted architectural assumptions, ...
Guy G. Lemieux, Stephen Dean Brown, Daniel Vranesi...
ISPD
1997
ACM
105views Hardware» more  ISPD 1997»
13 years 9 months ago
Regular layout generation of logically optimized datapaths
The inherent distortion of the structural regularity of VLSI datapaths after logic optimization has until now precluded dense regular layouts of optimized datapaths despite their ...
R. X. T. Nijssen, C. A. J. van Eijk
ISPD
1997
ACM
74views Hardware» more  ISPD 1997»
13 years 9 months ago
A matrix synthesis approach to thermal placement
— In this paper, we consider the thermal placement problem for gate arrays. We introduce a new combinatorial optimization problem, matrix synthesis problem (MSP), to model the th...
Chris C. N. Chu, D. F. Wong
ISPD
1997
ACM
186views Hardware» more  ISPD 1997»
13 years 9 months ago
EWA: exact wiring-sizing algorithm
The wire sizing problem under inequality Elmore delay constraints is known to be posynomial, hence convex under an exponential variable-transformation. There are formal methods fo...
Rony Kay, Gennady Bucheuv, Lawrence T. Pileggi