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ISSS
1998
IEEE
96views Hardware» more  ISSS 1998»
13 years 9 months ago
Fine Grain Incremental Rescheduling Via Architectural Retiming
With the decreasing feature sizes during VLSI fabrication and the dominance of interconnect delay over that of gates, control logic and wiring no longer have a negligible impact o...
Soha Hassoun
ISSS
1998
IEEE
130views Hardware» more  ISSS 1998»
13 years 9 months ago
Communication and Interface Synthesis on a Rapid Prototyping Hardware/Software Codesign System
In this paper, we propose the target board architecture of a rapid prototyping embedded system based on hardware software codesign. The target board contains a TMS320C30 DSP proce...
Yin-Tsung Hwang, Yuan-Hung Wang
ISSS
1998
IEEE
104views Hardware» more  ISSS 1998»
13 years 9 months ago
Synchronization Detection for Multi-Process Hierarchical Synthesis
Complex system specifications are often hierarchically composed of several subsystems. Each subsystem contains one or more processes. In order to provide optimization across diffe...
Oliver Bringmann, Wolfgang Rosenstiel, Dirk Reicha...
ISSS
1998
IEEE
124views Hardware» more  ISSS 1998»
13 years 9 months ago
Data-Path Synthesis of VLIW Video Signal Processors
This paper describes a methodology for synthesizing the data-path of a Very Long Instruction Word (VLIW) based Video Signal Processor (VSP). Offering both performance and programm...
Zhao Wu, Wayne Wolf
ISSS
1998
IEEE
120views Hardware» more  ISSS 1998»
13 years 9 months ago
Application of Instruction Analysis/Synthesis Tools to x86's Functional Unit Allocation
Designing a cost effective superscalar architecture for x86 compatible microprocessors is a challenging task in terms of both technical difficulty and commercial value. One of the...
Ing-Jer Huang, Ping-Huei Xie