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ISVLSI
2006
IEEE
150views VLSI» more  ISVLSI 2006»
13 years 11 months ago
Design and Analysis of a Low Power VLIW DSP Core
Power consumption has been the primary issue in processor design, with various power reduction strategies being adopted from system-level to circuitlevel. In order to develop a po...
Chan-Hao Chang, Diana Marculescu
ISVLSI
2006
IEEE
106views VLSI» more  ISVLSI 2006»
13 years 11 months ago
Self-Timed Thermally-Aware Circuits
Thermal management is becoming increasingly important in circuit designs with high power density. Circuits that overheat beyond specified operating conditions may suffer timing f...
David Fang, Filipp Akopyan, Rajit Manohar
ISVLSI
2006
IEEE
126views VLSI» more  ISVLSI 2006»
13 years 11 months ago
QUKU: A Two-Level Reconfigurable Architecture
FPGAs have been used for prototyping of ASICs, for low-volume ASIC replacement and for systems requiring in-field hardware upgrades. However, the potential to use dynamic reconfig...
Sunil Shukla, Neil W. Bergmann, Jürgen Becker
ISVLSI
2006
IEEE
137views VLSI» more  ISVLSI 2006»
13 years 11 months ago
Low Power Layered Space-Time Channel Detector Architecture for MIMO Systems
This paper presents the low power implementation of a Maximum Likelihood (ML) based detector used in the receiver part of a Multiple Input and Multiple Output (MIMO) systems. Low ...
T. Takahashi, Ahmet T. Erdogan, Tughrul Arslan, J....
ISVLSI
2006
IEEE
95views VLSI» more  ISVLSI 2006»
13 years 11 months ago
PLAs in Quantum-dot Cellular Automata
Abstract— Research in the fields of physics, chemistry and electronics has demonstrated that Quantum-dot Cellular Automata (QCA) is a viable alternative for nano-scale computing...
Xiaobo Sharon Hu, Michael Crocker, Michael T. Niem...