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ISVLSI
2007
IEEE
194views VLSI» more  ISVLSI 2007»
10 years 9 months ago
Congestion-Aware Task Mapping in NoC-based MPSoCs with Dynamic Workload
Ewerson Carvalho, Ney Laert Vilar Calazans, Fernan...
ISVLSI
2007
IEEE
126views VLSI» more  ISVLSI 2007»
10 years 9 months ago
MOTIM - A Scalable Architecture for Ethernet Switches
Erico Bastos, Everton Carara, Daniel V. Pigatto, N...
ISVLSI
2007
IEEE
100views VLSI» more  ISVLSI 2007»
10 years 9 months ago
Vector Processing Support for FPGA-Oriented High Performance Applications
In this paper, we propose and implement a vector processing system that includes two identical vector microprocessors embedded in two FPGA chips. Each vector microprocessor suppor...
Hongyan Yang, Shuai Wang, Sotirios G. Ziavras, Jie...
ISVLSI
2007
IEEE
107views VLSI» more  ISVLSI 2007»
10 years 9 months ago
A Quantum Algorithm for Finding Minimum Exclusive-Or Expressions
This paper presents a quantum algorithm for finding minimal ESCT (Exclusive-or Sum of Complex Terms) or ESOP (Exclusiveor Sum Of Products) expressions for any arbitrary incomplet...
Marinos Sampson, Dimitrios Voudouris, George K. Pa...
ISVLSI
2007
IEEE
131views VLSI» more  ISVLSI 2007»
10 years 9 months ago
Improving the Quality of Bounded Model Checking by Means of Coverage Estimation
Formal verification has become an important step in circuit and system design. A prominent technique is Bounded Model Checking (BMC) which is widely used in industry. In BMC it i...
Ulrich Kühne, Daniel Große, Rolf Drechs...
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