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ISVLSI
2008
IEEE
13 years 11 months ago
2008
IEEE
A structured ASIC has some arrays of pre-fabricated yet configurable logic blocks (CLBs) with/without a regular routing fabric. In this paper, we propose a standard cell like via-...
ISVLSI
2008
IEEE
13 years 11 months ago
2008
IEEE
As integrated circuits are scaled down it becomes difficult to maintain uniformity in process parameters across each individual die. The resulting performance variation requires ...
ISVLSI
2008
IEEE
13 years 11 months ago
2008
IEEE
A new hybrid CMOS-nanoscale circuit style has been developed that uses only one type of Field Effect Transistor (FET) in the logic portions of a design. This is enabled by CMOS pro...
ISVLSI
2008
IEEE
13 years 11 months ago
2008
IEEE
With the advent of nanometer technologies, the design size of integrated circuits is getting larger and the operation speed is getting faster. As a consequence, test cost is becom...
ISVLSI
2008
IEEE
13 years 11 months ago
2008
IEEE
In nanometer regime, the effects of process variations are dominating circuit performance, power and reliability of circuits. Hence, it is important to properly manage variation e...