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IWSOC
2003
IEEE
97views Hardware» more  IWSOC 2003»
13 years 10 months ago
Evaluating Template-Based Instruction Compression on Transport Triggered Architectures
In embedded systems, memory is one of the most expensive resources. Due to this, program code size has turned out to be one of the most critical design constraints. Code compressi...
Jari Heikkinen, Tommi Rantanen, Andrea G. M. Cilio...
IWSOC
2003
IEEE
137views Hardware» more  IWSOC 2003»
13 years 10 months ago
Hardware Partitioning Software for Dynamically Reconfigurable SoC Design
CAD tools support is essential in the success of today digital system design methodologies. Unfortunately, most of the classical design tools do not take into account the possibil...
Philippe Brunet, Camel Tanougast, Yves Berviller, ...
IWSOC
2003
IEEE
99views Hardware» more  IWSOC 2003»
13 years 10 months ago
Template Generation and Selection Algorithms
The availability of high-level design entry tooling is crucial for the viability of any reconfigurable SoC architecture. This paper presents a template generation method to extra...
Yuanqing Guo, Gerard J. M. Smit, Hajo Broersma, Pa...
IWSOC
2003
IEEE
104views Hardware» more  IWSOC 2003»
13 years 10 months ago
Incorporating Pattern Prediction Technique for Energy Efficient Filter Cache Design
: - A filter cache is proposed at a higher level than the L1 (main) cache in the memory hierarchy and is much smaller. The typical size of filter cache is of the order of 512 Bytes...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...