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MICRO
1999
IEEE
71views Hardware» more  MICRO 1999»
13 years 9 months ago
Selective Cache Ways: On-Demand Cache Resource Allocation
Increasing levels of microprocessor power dissipation call for new approaches at the architectural level that save energy by better matching of on-chip resources to application re...
David H. Albonesi
MICRO
1999
IEEE
104views Hardware» more  MICRO 1999»
13 years 9 months ago
Control Independence in Trace Processors
Branch mispredictions are a major obstacle to exploiting instruction-level parallelism, at least in part because all instructions after a mispredicted branch are squashed. However...
Eric Rotenberg, James E. Smith
MICRO
1999
IEEE
109views Hardware» more  MICRO 1999»
13 years 9 months ago
Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results
Recent studies on value locality reveal that many instructions are frequently executed with a small variety of inputs. This paper proposes an approach that integrates architecture...
Daniel A. Connors, Wen-mei W. Hwu
MICRO
1999
IEEE
138views Hardware» more  MICRO 1999»
13 years 9 months ago
Dynamic 3D Graphics Workload Characterization and the Architectural Implications
Although PC-class 3D graphics hardware has made significant strides in the last several years, the underlying architectural design principles are still generally considered as a b...
Tulika Mitra, Tzi-cker Chiueh
MICRO
1999
IEEE
98views Hardware» more  MICRO 1999»
13 years 9 months ago
Instruction Fetch Mechanisms for Multipath Execution Processors
Branch mispredictions can have a major performance impact on high-performance processors. Multipath execution has recently been introduced to help limit the misprediction penaltie...
Artur Klauser, Dirk Grunwald