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DATE
2008
IEEE
129views Hardware» more  DATE 2008»
13 years 11 months ago
Memory Technology for Extended Large-Scale Integration in Future Electronics Applications
Extending 2-D planar topologies in integrated circuits (ICs) to a 3-D implementation has the obvious benefits of reducing the overall footprint and average interconnection length,...
Dinesh Pamunuwa
DSD
2008
IEEE
124views Hardware» more  DSD 2008»
13 years 11 months ago
A Modular Approach to Model Heterogeneous MPSoC at Cycle Level
This paper proposes a system-level cycle-based framework to model and design heterogeneous Multiprocessor Systems on-Chip (MPSoC), called GRAPES. The approach features flexibilit...
Matteo Monchiero, Gianluca Palermo, Cristina Silva...
ITNG
2008
IEEE
13 years 11 months ago
Parallel FFT Algorithms on Network-on-Chips
This paper presents several parallel FFT algorithms with different degree of communication overhead for multiprocessors in Network-on-Chip(NoC) environment. Three different method...
Jun Ho Bahn, Jungsook Yang, Nader Bagherzadeh
TON
2008
87views more  TON 2008»
13 years 5 months ago
Large-scale network parameter configuration using an on-line simulation framework
As the Internet infrastructure grows to support a variety of services, its legacy protocols are being overloaded with new functions such as traffic engineering. Today, operators en...
Tao Ye, Hema Tahilramani Kaur, Shivkumar Kalyanara...
DAC
2008
ACM
14 years 6 months ago
On reliable modular testing with vulnerable test access mechanisms
In modular testing of system-on-a-chip (SoC), test access mechanisms (TAMs) are used to transport test data between the input/output pins of the SoC and the cores under test. Prio...
Lin Huang, Feng Yuan, Qiang Xu