Sciweavers

15 search results - page 2 / 3
» pacs 2000
Sort
View
PACS
2000
Springer
121views Hardware» more  PACS 2000»
13 years 8 months ago
Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power
Reducing the supply voltage to reduce dynamic power consumption in CMOS devices, inadvertently will lead to an exponential increase in leakage power dissipation. In this work we ex...
Stefanos Kaxiras, Zhigang Hu, Girija J. Narlikar, ...
PACS
2000
Springer
132views Hardware» more  PACS 2000»
13 years 8 months ago
An Adaptive Issue Queue for Reduced Power at High Performance
Increasing power dissipation has become a major constraint for future performance gains in the design of microprocessors. In this paper, we present the circuit design of an issue ...
Alper Buyuktosunoglu, Stanley Schuster, David Broo...
PACS
2000
Springer
118views Hardware» more  PACS 2000»
13 years 8 months ago
Ramp Up/Down Functional Unit to Reduce Step Power
Because the inductive noise Ldi/dt is induced by the power change and can have disastrous impact on the timing and reliability of the system, high-performance CPU designs are more ...
Zhenyu Tang, Norman Chang, Shen Lin, Weize Xie, O....
ASIACRYPT
2000
Springer
13 years 9 months ago
Commital Deniable Proofs and Electronic Campaign Finance
In a recent Stanford Law Review article, Ayres and Bulow [1] propose a radical anonymity-based solution to disrupt the “market” for monetary influence in political campaigns. ...
Matthew K. Franklin, Tomas Sander
PACS
2004
Springer
115views Hardware» more  PACS 2004»
13 years 10 months ago
Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization
Dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The delay ...
Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose, ...