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WCRE
2002
IEEE
13 years 11 months ago
Register Liveness Analysis for Optimizing Dynamic Binary Translation
Dynamic binary translators compile machine code from a source architecture to a target architecture at run time. Due to the hard time constraints of just-in-time compilation only ...
Mark Probst, Andreas Krall, Bernhard Scholz
FMSD
2002
107views more  FMSD 2002»
13 years 5 months ago
Verification of Out-Of-Order Processor Designs Using Model Checking and a Light-Weight Completion Function
We present a new technique for verification of complex hardware devices that allows both generality andahighdegreeofautomation.Thetechniqueisbasedonournewwayofconstructinga"li...
Sergey Berezin, Edmund M. Clarke, Armin Biere, Yun...
TMM
2002
81views more  TMM 2002»
13 years 5 months ago
Staggered push - a linearly scalable architecture for push-based parallel video servers
With the rapid performance improvements in low-cost PCs, it becomes increasingly practical and cost-effective to implement large-scale video-on-demand (VoD) systems around parallel...
Jack Y. B. Lee
TROB
2002
91views more  TROB 2002»
13 years 5 months ago
Time-domain passivity control of haptic interfaces
A patent pending, energy based, method is presented for controlling a haptic interface system to ensure stable contract under a wide variety of operating conditions. System stabil...
Blake Hannaford, Jee-Hwan Ryu
TVCG
2002
156views more  TVCG 2002»
13 years 5 months ago
A Hardware-Assisted Scalable Solution for Interactive Volume Rendering of Time-Varying Data
We present a scalable volume rendering technique that exploits lossy compression and low-cost commodity hardware to permit highly interactive exploration of time-varying scalar vol...
Eric B. Lum, Kwan-Liu Ma, John Clyne