— Integrated circuits have evolved to a stage where interconnections significantly limit their performance and functional complexity. We introduce a set of tools to perform high...
Rui Martins, Wolfgang Pyka, Rainer Sabelka, Siegfr...
This paper presents techniques for generating addresses for memories containing multiple arrays. Because these techniques rely on the inversion or rearrangement of address bits, t...
—We study the effect of the controller on the testability of sequential circuits composed of controllers and data paths. We show that even when all the loops of the circuit have ...
—This paper addresses, from a probabilistic point of view, the issue of switching activity estimation in combinational circuits under the zero-delay model. As the main theoretica...
—We give a denotational framework (a “meta model”) within which certain properties of models of computation can be compared. It describes concurrent processes in general term...