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TCAD
2002
121views more  TCAD 2002»
13 years 4 months ago
Robust Boolean reasoning for equivalence checking and functional property verification
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuits...
Andreas Kuehlmann, Viresh Paruthi, Florian Krohm, ...
TCAD
2002
91views more  TCAD 2002»
13 years 4 months ago
Retiming and clock scheduling for digital circuit optimization
Abstract--This paper investigates the application of simultaneous retiming and clock scheduling for optimizing synchronous circuits under setup and hold constraints. Two optimizati...
Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
TCAD
2002
139views more  TCAD 2002»
13 years 4 months ago
Digital filter synthesis based on an algorithm to generate all minimal signed digit representations
In this paper, the authors propose an algorithm to find all the minimal signed digit (MSD) representations of a constant and present an algorithm to synthesize digital filters base...
In-Cheol Park, Hyeong-Ju Kang
TCAD
2002
134views more  TCAD 2002»
13 years 4 months ago
DS-LFSR: a BIST TPG for low switching activity
A test pattern generator (TPG) for built-in self-test (BIST), which can reduce switching activity during test application, is proposed. The proposed TPG, called dual-speed LFSR (DS...
Seongmoon Wang, Sandeep K. Gupta
TCAD
2002
118views more  TCAD 2002»
13 years 4 months ago
Application-specific clustered VLIW datapaths: early exploration on a parameterized design space
Specialized clustered very large instruction word (VLIW) processors combined with effective compilation techniques enable aggressive exploitation of the high instruction-level para...
Viktor S. Lapinskii, Margarida F. Jacome, Gustavo ...