Low latency, application, specific multipliers are required for m,any DSP algorithms. Tree multipliers are an obvious answer to this requirement. However, tree architectures have ...
An area-eficzent systolic architecture for realtime, programmable-coeBcient jinite impulse response (FIR)filters is presented. A technique called pipelined clustering is introduce...
This paper discusses a Genetic Algorithm-based method of generating test vectorsfor detecting faults in combinational circuits. The GA-based approach combines the merits of two te...
High throughput and low latency designs are required in modern high performance systems, especially for signal processing applications. Existing logic families cannot provide both...
Debabrata Ghosh, S. K. Nandy, K. Parthasarathy, V....
It is well-known that varying architectural, technological and implementation aspects of embedded microprocessors, such as ARM, can produce widely differing performance and power ...