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VLSID
2002
IEEE
97views VLSI» more  VLSID 2002»
13 years 9 months ago
Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement
Power supply noise is a strong function of the switching activities of the circuit modules. Peak power supply noise can be significantly reduced by judiciously arranging the modu...
Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh
VLSID
2002
IEEE
207views VLSI» more  VLSID 2002»
14 years 5 months ago
Synthesis of High Performance Low Power Dynamic CMOS Circuits
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
Debasis Samanta, Nishant Sinha, Ajit Pal
VLSID
2002
IEEE
78views VLSI» more  VLSID 2002»
14 years 5 months ago
Optimization of Test Accesses with a Combined BIST and External Test Scheme
External pins for test are precious hardware resources because this number is strongly restricted. Cores are tested via test access mechanisms (TAMs) such as a test bus architectu...
Makoto Sugihara, Hiroto Yasuura
VLSID
2002
IEEE
151views VLSI» more  VLSID 2002»
14 years 5 months ago
Mode Selection and Mode-Dependency Modeling for Power-Aware Embedded Systems
Among the many techniques for system-level power management, it is not currently possible to guarantee timing constraints and have a comprehensive system model at the same time. S...
Dexin Li, Pai H. Chou, Nader Bagherzadeh
VLSID
2002
IEEE
142views VLSI» more  VLSID 2002»
14 years 5 months ago
Address Code and Arithmetic Optimizations for Embedded Systems
An important class of problems used widely in both the embedded systems and scientific domains perform memory intensive computations on large data sets. These data sets get to be ...
J. Ramanujam, Satish Krishnamurthy, Jinpyo Hong, M...