45 search results - page 9 / 9 » vlsid 2005 |
VLSID
2005
IEEE
2005
IEEE
Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model
13 years 11 months ago
One of the emerging challenges in formal property verification (FPV) technology is the problem of deciding whether sufficient properties have been written to cover the design in...
VLSID
2005
IEEE
13 years 11 months ago
2005
IEEE
The primary advantage of using 3D-FPGA over 2D-FPGA is that the vertical stacking of active layers reduce the Manhattan distance between the components in 3D-FPGA than when placed...
VLSID
2005
IEEE
13 years 11 months ago
2005
IEEE
During pseudorandom testing, a significant amount of energy and test application time is wasted for generating and for applying “useless” test vectors that do not contribute t...
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after...