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VTS
2005
IEEE
96views Hardware» more  VTS 2005»
13 years 11 months ago
Effective TARO Pattern Generation
TARO test patterns are transition fault test patterns that sensitize each transition fault to all of the outputs that can be reached from the fault location. We were not able to i...
Intaik Park, Ahmad A. Al-Yamani, Edward J. McClusk...
VTS
2005
IEEE
145views Hardware» more  VTS 2005»
13 years 11 months ago
Hardware Results Demonstrating Defect Detection Using Power Supply Signal Measurements
The power supply transient signal (IDDT) method that we propose for defect detection analyze regional signal variations introduced by defects at a set of power supply pads on the ...
Dhruva Acharyya, Jim Plusquellic
VTS
2005
IEEE
162views Hardware» more  VTS 2005»
13 years 11 months ago
Low-Cost Alternate EVM Test for Wireless Receiver Systems
† In digital radio applications, error-vector-magnitude (EVM) is the primary specification which quantifies the performance of digital modulation implemented in silicon. Producti...
Achintya Halder, Abhijit Chatterjee
VTS
2005
IEEE
96views Hardware» more  VTS 2005»
13 years 11 months ago
Pseudo-Functional Scan-based BIST for Delay Fault
This paper presents a pseudo-functional BIST scheme that attempts to minimize the over-testing problem of logic BIST for delay and crosstalk-induced failures. The over-testing pro...
Yung-Chieh Lin, Feng Lu, Kwang-Ting Cheng
VTS
2005
IEEE
102views Hardware» more  VTS 2005»
13 years 11 months ago
Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance
Nanometer circuits are highly susceptible to soft errors generated by alpha-particle or atmospheric neutron strikes to circuit nodes. The reasons for the high susceptibility are t...
Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhij...