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EURODAC
1995
IEEE
101views VHDL» more  EURODAC 1995»
13 years 8 months ago
Exploiting power-up delay for sequential optimization
Recent work has identified the notion of safe replacement for sequential synchronousdesigns that may not have reset hardware or even explicitly known initial states. Safe replace...
Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K....