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    ISCAS
    2008
    IEEE
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    A low-area interconnect architecture for chip multiprocessors
    13 years 11 months ago
    A low-area interconnect architecture for chip multiprocessors
    Download  www.ece.ucdavis.edu
    — A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost and flexible routing capability. To achieve a low area cost, th...
    Zhiyi Yu, Bevan M. Baas
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