Sciweavers

DATE
2008
IEEE
109views Hardware» more  DATE 2008»
13 years 11 months ago
Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation
— Market and customer demands have continued to push the limits of CMOS performance. At-speed test has become a common method to ensure these high performance chips are being shi...
Jeremy Lee, Sumit Narayan, Mike Kapralos, Mohammad...