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12
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ISCAS
2008
IEEE
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ISCAS 2008
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A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop
13 years 11 months ago
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lpsoc.eic.nctu.edu.tw
—A 333MHz-1GHz all-digital multiphase delay-locked loop with precise multi-phase output has been designed with TSMC 130nm CMOS technology model. A modified binary search algorith...
Li-Pu Chuang, Ming-Hung Chang, Po-Tsang Huang, Chi...
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