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    SRAM Read/Write Margin Enhancements Using FinFETs
    12 years 11 months ago
    SRAM Read/Write Margin Enhancements Using FinFETs
    Download  bwrc.eecs.berkeley.edu
    Process-induced variations and sub-threshold leakage in bulk-Si technology limit the scaling of SRAM into sub-32 nm nodes. New device architectures are being considered to improve ...
    Andrew Carlson, Zheng Guo, Sriram Balasubramanian,...
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