Sciweavers

ICCD
2003
IEEE
137views Hardware» more  ICCD 2003»
14 years 2 months ago
Dynamic Thread Resizing for Speculative Multithreaded Processors
There is a growing interest in the use of speculative multithreading to speed up the execution of a program. In speculative multithreading model, threads are extracted from a sequ...
Mohamed M. Zahran, Manoj Franklin
ICCD
2003
IEEE
141views Hardware» more  ICCD 2003»
14 years 2 months ago
Structured ASICs: Opportunities and Challenges
There is currently a huge gap between the two main technologies used to implement custom digital integrated circuit (IC) designs. At one end of the spectrum are field programmable...
Behrooz Zahiri
ICCD
2003
IEEE
127views Hardware» more  ICCD 2003»
14 years 2 months ago
Structural Detection of Symmetries in Boolean Functions
Functional symmetries provide significant benefits for multiple tasks in synthesis and verification. Many applications require the manual specification of symmetries using spe...
Guoqiang Wang, Andreas Kuehlmann, Alberto L. Sangi...
ICCD
2003
IEEE
113views Hardware» more  ICCD 2003»
14 years 2 months ago
Exploiting Microarchitectural Redundancy For Defect Tolerance
Continued advancements in fabrication technology and reductions in feature size create challenges in maintaining both manufacturing yield rates and long-term reliability of device...
Premkishore Shivakumar, Stephen W. Keckler, Charle...
ICCD
2003
IEEE
177views Hardware» more  ICCD 2003»
14 years 2 months ago
SAT-Based Algorithms for Logic Minimization
This paper introduces a new method for two-level logic minimization. Unlike previous approaches, the new method uses a SAT solver as an underlying engine. While the overall minimi...
Samir Sapra, Michael Theobald, Edmund M. Clarke
ICCD
2003
IEEE
111views Hardware» more  ICCD 2003»
14 years 2 months ago
Routed Inter-ALU Networks for ILP Scalability and Performance
Modern processors rely heavily on broadcast networks to bypass instruction results to dependent instructions in the pipeline. However, as clock rates increase, architectures get w...
Karthikeyan Sankaralingam, Vincent Ajay Singh, Ste...
ICCD
2003
IEEE
115views Hardware» more  ICCD 2003»
14 years 2 months ago
Reducing Compilation Time Overhead in Compiled Simulators
Compiled simulation is a well known technique for improving the performance of instruction set simulators at the cost of compilation time. However the compilation time overhead ma...
Mehrdad Reshadi, Nikil D. Dutt
ICCD
2003
IEEE
167views Hardware» more  ICCD 2003»
14 years 2 months ago
Virtual Page Tag Reduction for Low-power TLBs
We present a methodology for a power-optimized, software-controlled Translation Lookaside Buffer (TLB) organization. A highly reduced number of Virtual Page Number (VPN) bits suf...
Peter Petrov, Alex Orailoglu
ICCD
2003
IEEE
107views Hardware» more  ICCD 2003»
14 years 2 months ago
Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Context Switches
Embedded processors like Intel’s XScale use dynamic branch prediction to improve performance. Due to the presence of context switches, the accuracy of these predictors is reduce...
Sudeep Pasricha, Alexander V. Veidenbaum
ICCD
2003
IEEE
134views Hardware» more  ICCD 2003»
14 years 2 months ago
An Efficient Algorithm for Calculating the Worst-case Delay due to Crosstalk
Analyzing the effect of crosstalk on delay is critical for high performance circuits. The major bottleneck in performing crosstalkinduced delay analysis is the high computational ...
Venkatesan Rajappan, Sachin S. Sapatnekar