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2003
IEEE

Exploiting Microarchitectural Redundancy For Defect Tolerance

11 years 1 months ago
Exploiting Microarchitectural Redundancy For Defect Tolerance
Continued advancements in fabrication technology and reductions in feature size create challenges in maintaining both manufacturing yield rates and long-term reliability of devices. Methods based on defect detection and reduction may not offer a scalable solution due to cost of eliminating contaminants in the manufacturing process and increasing chip complexity. This paper proposes to use the inherent redundancy available in existing and future chip microarchitectures to improve yield and enable graceful performance degradation in fail-in-place systems. We introduce a new yield metric called performance averaged yield (  ¢¡¤£¢¥ ) which accounts both for fully functional chips and those that exhibit some performance degradation. Our results indicate that at 250nm we are able to increase the   ¡¤£¢¥ of a uniprocessor with only redundant rows in its caches from a base value of 85% to 98% using microarchitectural redundancy. Given constant chip area, shrinking feature sizes i...
Premkishore Shivakumar, Stephen W. Keckler, Charle
Added 16 Mar 2010
Updated 16 Mar 2010
Type Conference
Year 2003
Where ICCD
Authors Premkishore Shivakumar, Stephen W. Keckler, Charles R. Moore, Doug Burger
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