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ASPDAC
1998
ACM
49views Hardware» more  ASPDAC 1998»
13 years 9 months ago
Unrolling Loops With Indeterminate Loop Counts in System Level Pipelines
This paper describes the unrolling of loops with indeterminate loop counts in system level pipelines. Two methods are discussed in this paper. The first method is the varied latenc...
Hui Guo, Sri Parameswaran
ASPDAC
1998
ACM
86views Hardware» more  ASPDAC 1998»
13 years 9 months ago
Hierarchy - A CHDStd Tool for the Coming Deep Submicron Complex Design Crisis
Abstract -- This paper describes the use of a hierarchical design representation standard, CHDStd, as part of the architecture of the Chip Hierarchical Design System (CHDS). Detail...
S. Grout, G. Ledenbach, R. G. Bushroe, P. Fisher, ...
ASPDAC
1998
ACM
81views Hardware» more  ASPDAC 1998»
13 years 9 months ago
A Heuristic Algorithm to Design AND-OR-EXOR Three-Level Networks
—An AND-OR-EXOR network, where the output EXOR gate has only two inputs, is one of the simplest three-level architecture. This network realizes an EXOR of two sum-of-products exp...
Debatosh Debnath, Tsutomu Sasao
ASPDAC
1998
ACM
96views Hardware» more  ASPDAC 1998»
13 years 9 months ago
A Low Power 2-D DCT Chip Design Using Direct 2-D Algorithm
Liang-Gee Chen, Juing-Ying Jiu, Hao-Chieh Chang, Y...
ASPDAC
1998
ACM
80views Hardware» more  ASPDAC 1998»
13 years 9 months ago
Air-Pressure-Model-Based Fast Algorithms for General Floorplan
Tomonori Izumi, Atsushi Takahashi, Yoji Kajitani
ASPDAC
1998
ACM
86views Hardware» more  ASPDAC 1998»
13 years 9 months ago
Parallelization in Co-Compilation for Configurable Accelerators
— The paper introduces a novel co-compiler and its “vertical” parallelization method, including a general model for co-operating host/accelerator platforms and a new parallel...
Jürgen Becker, Reiner W. Hartenstein, Michael...
ASPDAC
1998
ACM
79views Hardware» more  ASPDAC 1998»
13 years 9 months ago
Simultaneous Wire Sizing and Wire Spacing in Post-Layout Performance Optimization
- In this paper, we study the wire sizing and wire spacing problem for post-layout performance optimization under Elmore delay model. Both ground capacitance and coupled capacitanc...
Jiang-An He, Hideaki Kobayashi