Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

8

ASPDAC
1998
ACM

favoriteEmaildiscussreport

96views Hardware» more ASPDAC 1998»

A Low Power 2-D DCT Chip Design Using Direct 2-D Algorithm

13 years 8 months ago

A Low Power 2-D DCT Chip Design Using Direct 2-D Algorithm

Download www.vtvt.ece.vt.edu

Liang-Gee Chen, Juing-Ying Jiu, Hao-Chieh Chang, Y

Real-time Traffic

ASPDAC 1998 | Hardware |

claim paper

Related Content

» A BuiltIn SelfRepair Scheme for Semiconductor Memories with 2D Redundancy

» Orthogonal Greedy Coupling A New Optimization Approach to 2D FPGA Routing

» Fast multicore based multimodal registration of 2D crosssections and 3D datasets

» Process variation tolerant low power DCT architecture

» Dynamic bitwidth adaptation in DCT image quality versus computation energy tradeoff

» Custom Processor Design Using NISC A CaseStudy on DCT algorithm

» DCTbased motion estimation

» Congestionaware power grid optimization for 3D circuits using MIM and CMOS decoupling capa...

» A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applic...

Post Info
More Details (n/a)

Added	05 Aug 2010
Updated	05 Aug 2010
Type	Conference
Year	1998
Where	ASPDAC
Authors	Liang-Gee Chen, Juing-Ying Jiu, Hao-Chieh Chang, Yung-Pin Lee, Chung-Wei Ku

Comments (0)