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    GLVLSI
    2008
    IEEE
    112views VLSI» more  GLVLSI 2008»
    Instruction cache leakage reduction by changing register operands and using asymmetric sram cells
    13 years 11 months ago
    Instruction cache leakage reduction by changing register operands and using asymmetric sram cells
    Download  qir.kyushu-u.ac.jp
    Share of leakage in cache memories is increasing with technology scaling. Studies show that most stored bits in instruction caches are zero, and hence, asymmetric SRAM cells which...
    Maziar Goudarzi, Tohru Ishihara
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