Instruction cache leakage reduction by changing register operands and using asymmetric sram cells

Share of leakage in cache memories is increasing with technology scaling. Studies show that most stored bits in instruction caches are zero, and hence, asymmetric SRAM cells which dissipate less leakage when storing 0, effectively reduce leakage with negligible performance penalty. We show that by carefully choosing register operands of instructions, it is possible to further increase the number of 0 bits, and hence, increase leakage savings in instruction cache. This compiler technique is performed off-line and introduces absolutely no delay penalty since processor registers are all the same. Experimental results of our benchmarks show up to 33% (averaging 30.35%) improvement in leakage. Categories and Subject Descriptors B.3.1 [Semiconductor Memories]: Static memory (SRAM). B.3.2 [Design Styles]: Cache memories. D.3.4 [Processors]: Compilers, Optimization. General Terms Algorithms, Measurement, Design, Experimentation.

• Type: Conference
• Year: 2008
• Where: GLVLSI
• Authors: Maziar Goudarzi, Tohru Ishihara
• Keywords: Asymmetric Sram Cells, Cache Memories, GLVLSI 2008, Instruction Cache, VLSI