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ASYNC
2005
IEEE
79views Hardware» more  ASYNC 2005»
9 years 8 months ago
A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip
Guaranteed services (GS) are important in that they provide predictability in the complex dynamics of shared communication structures. This paper discusses the implementation of G...
Tobias Bjerregaard, Jens Sparsø
ASYNC
2005
IEEE
132views Hardware» more  ASYNC 2005»
10 years 12 days ago
High Level Synthesis of Timed Asynchronous Circuits
This paper proposes applying a logic synthesis approach to high level synthesis from SpecC speciļ¬cations to timed asynchronous gate-level circuits. The state-based logic synthes...
Tomohiro Yoneda, Atsushi Matsumoto, Manabu Kato, C...
ASYNC
2005
IEEE
174views Hardware» more  ASYNC 2005»
10 years 12 days ago
Delay Insensitive Encoding and Power Analysis: A Balancing Act
Unprotected cryptographic hardware is vulnerable to a side-channel attack known as Differential Power Analysis (DPA). This attack exploits data-dependent power consumption of a co...
Konrad J. Kulikowski, Ming Su, Alexander B. Smirno...
ASYNC
2005
IEEE
118views Hardware» more  ASYNC 2005»
10 years 12 days ago
Modeling and Verifying Circuits Using Generalized Relative Timing
We propose a novel technique for modeling and verifying timed circuits based on the notion of generalized relative timing. Generalized relative timing constraints can express not ...
Sanjit A. Seshia, Randal E. Bryant, Kenneth S. Ste...
ASYNC
2005
IEEE
96views Hardware» more  ASYNC 2005»
10 years 12 days ago
GasP Control for Domino Circuits
We present two novel asynchronous control circuits for domino pipelines. The control circuits are based on GasP circuits, have a minimum cycle time of six gate delays, and compare...
Jo C. Ebergen, Jonathan Gainsley, Jon K. Lexau, Iv...
ASYNC
2005
IEEE
71views Hardware» more  ASYNC 2005»
10 years 12 days ago
Proximity Communication and Time
Robert J. Drost, Ivan E. Sutherland
ASYNC
2005
IEEE
97views Hardware» more  ASYNC 2005»
10 years 12 days ago
Self-Timed Circuitry for Global Clocking
We present an apparatus used to distribute a timing reference or clock across the extent of a digital system. Selftimed circuitry both generates and distributes a clock signal, wh...
Scott Fairbanks, Simon W. Moore
ASYNC
2005
IEEE
90views Hardware» more  ASYNC 2005»
10 years 12 days ago
SEU-Tolerant QDI Circuits
This paper addresses the issue of Single-Event Upset (SEU) in quasi delay-insensitive (QDI) asynchronous circuits. We show that an SEU can cause abnormal computations in QDI circu...
Wonjin Jang, Alain J. Martin
ASYNC
2005
IEEE
142views Hardware» more  ASYNC 2005»
10 years 12 days ago
An Asynchronous Router for Multiple Service Levels Networks on Chip
Networks on Chip that can guarantee Quality of Service (QNoC) are based on special routers that can support multiple service levels. GALS SoCs call for asynchronous NoC implementa...
Rostislav (Reuven) Dobkin, Victoria Vishnyakov, Ey...
ASYNC
2005
IEEE
112views Hardware» more  ASYNC 2005»
10 years 12 days ago
Request-Driven GALS Technique for Wireless Communication System
A Globally Asynchronous - Locally Synchronous (GALS) technique for application in wireless communication systems is proposed and evaluated. The GALS wrappers are based on a reques...
Milos Krstic, Eckhard Grass, Christian Stahl
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