ASYNC
2007
IEEE
13 years 8 months ago
2007
IEEE
Few formal verification techniques are currently available for asynchronous designs. In this paper, we describe a new approach for the formal verification of asynchronous architec...
ASYNC
2007
IEEE
13 years 11 months ago
2007
IEEE
ASYNC
2007
IEEE
13 years 11 months ago
2007
IEEE
ASYNC
2007
IEEE
13 years 11 months ago
2007
IEEE
ASYNC
2007
IEEE
13 years 11 months ago
2007
IEEE
On-chip high-bandwidth sampling circuits supplement traditional test and debug techniques by non-invasively probing analog voltages for off-chip measurement. Existing circuits rel...
ASYNC
2007
IEEE
13 years 11 months ago
2007
IEEE
ASYNC
2007
IEEE
13 years 11 months ago
2007
IEEE
A high data rate asynchronous bit-serial link for long-range on-chip communication is presented. The data bit cycle time is equal to a single gate delay, enabling 67Gbps throughpu...
ASYNC
2007
IEEE
13 years 11 months ago
2007
IEEE
ASYNC
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper reports results of a study on pulse signaling. In pulse signaling, components communicate by means of pulses instead of voltage transitions. The functionality of the co...
ASYNC
2007
IEEE
13 years 11 months ago
2007
IEEE
Future deep sub-micron technologies will be characterized by large parametric variations, which could make asynchronous design an attractive solution for use on large scale. Howev...