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ICCD
1997
IEEE
90views Hardware» more  ICCD 1997»
13 years 8 months ago
TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model
Asynchronous design has a potential of solving many difficulties, such as clock skew and power consumption, which synchronous counterpart suffers with current and future VLSI tech...
Akihiro Takamura, Masashi Kuwako, Masashi Imai, Ta...
ICCD
1997
IEEE
158views Hardware» more  ICCD 1997»
13 years 8 months ago
Practical Advances in Asynchronous Design
Asynchronous systems are being viewed as an increasingly viable alternative to purely synchronous systems. This paper gives an overview of the current state of the art in practica...
Erik Brunvand, Steven M. Nowick, Kenneth Y. Yun
ECOWS
2006
Springer
13 years 8 months ago
Formal Modelling and Verification of an Asynchronous Extension of SOAP
Current web services are largely based on a synchronous request-response model that uses the Simple Object Access Protocol SOAP. Next-generation telecommunication networks, on the...
Maurice H. ter Beek, Stefania Gnesi, Franco Mazzan...
ECOOPWEXCEPTION
2006
Springer
13 years 8 months ago
Exception Handling and Asynchronous Active Objects: Issues and Proposal
Asynchronous Active Objects (AAOs), primarily exemplied by actors [1], nowadays exist in many forms (various kinds of actors, agents and components) and are more and more used beca...
Christophe Dony, Christelle Urtado, Sylvain Vautti...
CHES
2006
Springer
205views Cryptology» more  CHES 2006»
13 years 8 months ago
Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks
Balanced dynamic dual-rail gates and asynchronous circuits have been shown, if implemented correctly, to have natural and efficient resistance to side-channel attacks. Despite thei...
Konrad J. Kulikowski, Alexander B. Smirnov, Alexan...
DSN
2004
IEEE
13 years 8 months ago
Fault Detection and Isolation Techniques for Quasi Delay-Insensitive Circuits
This paper presents a novel circuit fault detection and isolation technique for quasi delay-insensitive asynchronous circuits. We achieve fault isolation by a combination of physi...
Christopher LaFrieda, Rajit Manohar
ASYNC
2004
IEEE
121views Hardware» more  ASYNC 2004»
13 years 8 months ago
Static Tokens: Using Dataflow to Automate Concurrent Pipeline Synthesis
We describe a new intermediate compiler representation, static token form, that is suitable for dataflow-style synthesis of high-level asynchronous specifications. Static token fo...
John Teifel, Rajit Manohar
CASES
2007
ACM
13 years 8 months ago
Performance-driven syntax-directed synthesis of asynchronous processors
The development of robust and efficient synthesis tools is important if asynchronous design is to gain more widespread acceptance. Syntax-directed translation is a powerful synthe...
Luis A. Plana, Doug A. Edwards, Sam Taylor, Luis A...
ASYNC
2007
IEEE
129views Hardware» more  ASYNC 2007»
13 years 8 months ago
Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip
Few formal verification techniques are currently available for asynchronous designs. In this paper, we describe a new approach for the formal verification of asynchronous architec...
Gwen Salaün, Wendelin Serwe, Yvain Thonnart, ...
COMPCON
1994
IEEE
13 years 9 months ago
AMULET1: A Micropipelined ARM
A fully asynchronous implementation of the ARM microprocessor has been developed in order to investigate the potential of asynchronous logic for low-power applications. The work d...
Stephen B. Furber, P. Day, Jim D. Garside, N. C. P...