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HIPC
2009
Springer
8 years 4 months ago
Distance-aware round-robin mapping for large NUCA caches
In many-core architectures, memory blocks are commonly assigned to the banks of a NUCA cache by following a physical mapping. This mapping assigns blocks to cache banks in a round-...
Alberto Ros, Marcelo Cintra, Manuel E. Acacio, Jos...
ISLPED
2003
ACM
87views Hardware» more  ISLPED 2003»
8 years 11 months ago
On load latency in low-power caches
Many of the recently proposed techniques to reduce power consumption in caches introduce an additional level of nondeterminism in cache access latency. Due to this additional late...
Soontae Kim, Narayanan Vijaykrishnan, Mary Jane Ir...
MICRO
2003
IEEE
106views Hardware» more  MICRO 2003»
8 years 11 months ago
Near-Optimal Precharging in High-Performance Nanoscale CMOS Caches
High-performance caches statically pull up the bitlines in all cache subarrays to optimize cache access latency. Unfortunately, such an architecture results in a significant wast...
Se-Hyun Yang, Babak Falsafi
ICCD
2005
IEEE
101views Hardware» more  ICCD 2005»
9 years 3 months ago
Restrictive Compression Techniques to Increase Level 1 Cache Capacity
Increasing cache latencies limit L1 cache sizes. In this paper we investigate restrictive compression techniques for level 1 data cache, to avoid an increase in the cache access l...
Prateek Pujara, Aneesh Aggarwal
ICCD
2006
IEEE
92views Hardware» more  ICCD 2006»
9 years 3 months ago
Fast Speculative Address Generation and Way Caching for Reducing L1 Data Cache Energy
— L1 data caches in high-performance processors continue to grow in set associativity. Higher associativity can significantly increase the cache energy consumption. Cache access...
Dan Nicolaescu, Babak Salamat, Alexander V. Veiden...
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