ISMVL
2005
IEEE
13 years 10 months ago
2005
IEEE
In this paper, we propose three novel cache models using Multiple-Valued Logic (MVL) paradigm to reduce the cache data storage area and cache energy consumption for embedded syste...
ICCD
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper investigates some power efficient data cache designs that try to significantly reduce the cache energy consumption, both static and dynamic, with a minimal impact in pe...
ICCD
2006
IEEE
14 years 1 months ago
2006
IEEE
— L1 data caches in high-performance processors continue to grow in set associativity. Higher associativity can significantly increase the cache energy consumption. Cache access...