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IJHPCA
2006
122views more  IJHPCA 2006»
8 years 9 months ago
A New Hardware Monitor Design to Measure Data Structure-Specific Cache Eviction Information
In this paper, we propose a hardware performance monitor that provides support not only for measuring cache misses and the addresses associated with them, but also for determining...
Bryan R. Buck, Jeffrey K. Hollingsworth
CN
2006
64views more  CN 2006»
8 years 9 months ago
Piggybacking related domain names to improve DNS performance
In this paper, we present a novel approach to exploit the relationships among domain names to improve the cache hit rate for a local DNS server. Using these relationships, an auth...
Hao Shang, Craig E. Wills
SODA
2003
ACM
127views Algorithms» more  SODA 2003»
8 years 10 months ago
The set-associative cache performance of search trees
We consider the costs of access to data stored in search trees assuming that those memory accesses are managed with a cache. Our cache memory model is two-level, has a small degre...
James D. Fix
CCCG
2007
8 years 11 months ago
Cache-Oblivious Output-Sensitive Two-Dimensional Convex Hull
We consider the problem of two-dimensional outputsensitive convex hull in the cache-oblivious model. That is, we are interested in minimizing the number of cache faults caused whe...
Peyman Afshani, Arash Farzan
CODES
2005
IEEE
8 years 11 months ago
An efficient direct mapped instruction cache for application-specific embedded systems
Caches may consume half of a microprocessor’s total power and cache misses incur accessing off-chip memory, which is both time consuming and energy costly. Therefore, minimizing...
Chuanjun Zhang
CF
2006
ACM
8 years 11 months ago
Intermediately executed code is the key to find refactorings that improve temporal data locality
The growing speed gap between memory and processor makes an efficient use of the cache ever more important to reach high performance. One of the most important ways to improve cac...
Kristof Beyls, Erik H. D'Hollander
LCTRTS
2010
Springer
8 years 11 months ago
Resilience analysis: tightening the CRPD bound for set-associative caches
In preemptive real-time systems, scheduling analyses need—in addition to the worst-case execution time—the context-switch cost. In case of preemption, the preempted and the pr...
Sebastian Altmeyer, Claire Maiza, Jan Reineke
MICRO
1995
IEEE
108views Hardware» more  MICRO 1995»
9 years 29 days ago
SPAID: software prefetching in pointer- and call-intensive environments
Software prefetching, typically in the context of numericor loop-intensive benchmarks, has been proposed as one remedy for the performance bottleneck imposed on computer systems b...
Mikko H. Lipasti, William J. Schmidt, Steven R. Ku...
CGO
2004
IEEE
9 years 1 months ago
Static Identification of Delinquent Loads
The effective use of processor caches is crucial to the performance of applications. It has been shown that cache misses are not evenly distributed throughout a program. In applic...
Vlad-Mihai Panait, Amit Sasturkar, Weng-Fai Wong
ASPLOS
1992
ACM
9 years 1 months ago
Design and Evaluation of a Compiler Algorithm for Prefetching
Software-controlled data prefetching is a promising technique for improving the performance of the memory subsystem to match today's high-performance processors. While prefet...
Todd C. Mowry, Monica S. Lam, Anoop Gupta
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