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    FPL
    2008
    Springer
    104views Hardware» more  FPL 2008»
    A technique for minimizing power during FPGA placement
    13 years 6 months ago
    A technique for minimizing power during FPGA placement
    Download  sifaka.uwaterloo.ca
    This paper considers the implementation of an annealing technique for dynamic power reduction in FPGAs. The proposed method comprises a power-aware objective function for placemen...
    Kristofer Vorwerk, Madhu Raman, Julien Dunoyer, Ya...
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