Sciweavers

CF
2010
ACM
13 years 9 months ago
Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cach
As the number of transistors on a chip doubles with every technology generation, the number of on-chip cores also increases rapidly, making possible in a foreseeable future to des...
Pierre Michaud, Yiannakis Sazeides, André S...
CF
2010
ACM
13 years 9 months ago
Scalable simulation of complex network routing policies
Andrew Ian Stone, Steve DiBenedetto, Michelle Mill...
CF
2010
ACM
13 years 9 months ago
On-chip communication and synchronization mechanisms with cache-integrated network interfaces
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
Stamatis G. Kavadias, Manolis Katevenis, Michail Z...
CF
2010
ACM
13 years 9 months ago
Enabling a highly-scalable global address space model for petascale computing
Over the past decade, the trajectory to the petascale has been built on increased complexity and scale of the underlying parallel architectures. Meanwhile, software developers hav...
Vinod Tipparaju, Edoardo Aprà, Weikuan Yu, ...
CF
2010
ACM
13 years 9 months ago
Interval-based models for run-time DVFS orchestration in superscalar processors
We develop two simple interval-based models for dynamic superscalar processors. These models allow us to: i) predict with great accuracy performance and power consumption under va...
Georgios Keramidas, Vasileios Spiliopoulos, Stefan...
CF
2010
ACM
13 years 9 months ago
ERBIUM: a deterministic, concurrent intermediate representation for portable and scalable performance
Tuning applications for multi-core systems involve subtle concepts and target-dependent optimizations. New languages are being designed to express concurrency and locality without...
Cupertino Miranda, Philippe Dumont, Albert Cohen, ...
CF
2010
ACM
13 years 9 months ago
EXACT: explicit dynamic-branch prediction with active updates
Branches that depend directly or indirectly on load instructions are a leading cause of mispredictions by state-of-the-art branch predictors. For a branch of this type, there is a...
Muawya Al-Otoom, Elliott Forbes, Eric Rotenberg
CF
2010
ACM
13 years 9 months ago
Load balancing using dynamic cache allocation
Supercomputers need a huge budget to be built and maintained. To maximize the usage of their resources, application developers spend time to optimize the code of the parallel appl...
Miquel Moretó, Francisco J. Cazorla, Rizos ...