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    GLVLSI
    2005
    IEEE
    132views VLSI» more  GLVLSI 2005»
    FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks
    13 years 10 months ago
    FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks
    Download  hvg.ece.concordia.ca
    In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
    Abdallah Merhebi, Otmane Aït Mohamed
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