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ESSCIRC
2011
93views more  ESSCIRC 2011»
12 years 4 months ago
12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 volta
— Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations wi...
Atsushi Muramatsu, Tadashi Yasufuku, Masahiro Nomu...
APCCAS
2006
IEEE
296views Hardware» more  APCCAS 2006»
13 years 11 months ago
2PADCL: Two Phase drive Adiabatic Dynamic CMOS Logic
Abstract— This paper proposes a novel two-phase drive adiabatic dynamic CMOS logic circuit (2PADCL). The proposed 2PADCL uses two complementary sinusoidal power supply clocks and...
Yasuhiro Takahashi, Youhei Fukuta, Toshikazu Sekin...