Sciweavers

DATE
2003
IEEE
84views Hardware» more  DATE 2003»
13 years 10 months ago
Micro-Network for SoC: Implementation of a 32-Port SPIN network
We present a physical imrplementation of a 32-ports SPIN micro-network. For a 0.13 micron CMOS process, the total area is 4.6 ¢£¢¥¤ , for a cumulated bandwidth of about 100 G...
Adrijean Andriahantenaina, Alain Greiner
ISCAS
2005
IEEE
175views Hardware» more  ISCAS 2005»
13 years 10 months ago
New curvature-compensation technique for CMOS bandgap reference with sub-1-V operation
—A new sub-1-V curvature-compensated CMOS bandgap reference, which utilizes the temperature-dependent currents generated from the parasitic n-p-n and p-n-p bipolar junction trans...
Ming-Dou Ker, Jung-Sheng Chen, Ching-Yun Chu