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HPCA
2011
IEEE
10 years 5 months ago
MOPED: Orchestrating interprocess message data on CMPs
Future CMPs will combine many simple cores with deep cache hierarchies. With more cores, cache resources per core are fewer, and must be shared carefully to avoid poor utilization...
Junli Gu, Steven S. Lumetta, Rakesh Kumar, Yihe Su...
ASPLOS
2011
ACM
10 years 5 months ago
Hardware acceleration of transactional memory on commodity systems
The adoption of transactional memory is hindered by the high overhead of software transactional memory and the intrusive design changes required by previously proposed TM hardware...
Jared Casper, Tayo Oguntebi, Sungpack Hong, Nathan...
ISCA
2011
IEEE
290views Hardware» more  ISCA 2011»
10 years 5 months ago
Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks
To meet the demand for more powerful high-performance shared-memory servers, multiprocessor systems must incorporate efficient and scalable cache coherence protocols, such as thos...
Blas Cuesta, Alberto Ros, María Engracia G&...
TPDS
2008
134views more  TPDS 2008»
11 years 1 months ago
Extending the TokenCMP Cache Coherence Protocol for Low Overhead Fault Tolerance in CMP Architectures
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On th...
Ricardo Fernández Pascual, José M. G...
DSD
2008
IEEE
147views Hardware» more  DSD 2008»
11 years 3 months ago
A Low-Cost Cache Coherence Verification Method for Snooping Systems
Due to modern technology trends such as decreasing feature sizes and lower voltage levels, fault tolerance is becoming increasingly important in computing systems. Shared memory i...
Demid Borodin, Ben H. H. Juurlink
HIPEAC
2010
Springer
11 years 3 months ago
Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions
Abstract. Customizable processors augmented with application-specific Instruction Set Extensions (ISEs) have begun to gain traction in recent years. The most effective ISEs include...
Theo Kluter, Samuel Burri, Philip Brisk, Edoardo C...
ISCA
1995
IEEE
147views Hardware» more  ISCA 1995»
11 years 5 months ago
Dynamic Self-Invalidation: Reducing Coherence Overhead in Shared-Memory Multiprocessors
This paper introduces dynamic self-invalidation (DSI), a new technique for reducing cache coherence overhead in shared-memory multiprocessors. DSI eliminates invalidation messages...
Alvin R. Lebeck, David A. Wood
ANSS
1995
IEEE
11 years 5 months ago
Algorithms for categorizing multiprocessor communication under invalidate and update-based coherence protocols
In this paper we present simulation algorithmsthat characterize the main sources of communication generated by parallel applications under both invalidate and updatebased cache co...
Ricardo Bianchini, Leonidas I. Kontothanassis
DSD
2009
IEEE
136views Hardware» more  DSD 2009»
11 years 5 months ago
An Evaluation of Behaviors of S-NUCA CMPs Running Scientific Workload
Modern systems are able to put two or more processors on the same die (Chip Multiprocessors, CMP), each with its private caches, while the last level caches can be either private ...
Pierfrancesco Foglia, Francesco Panicucci, Cosimo ...
ICPP
1993
IEEE
11 years 5 months ago
A Hybrid Shared Memory/Message Passing Parallel Machine
Current and emerging high-performance parallel computer architectures generally implement one of two types of communication mechanisms: shared memory (SM) or message passing (MP)....
Matthew Frank, Mary K. Vernon
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