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    GLVLSI
    2007
    IEEE
    328views VLSI» more  GLVLSI 2007»
    New timing and routability driven placement algorithms for FPGA synthesis
    13 years 11 months ago
    New timing and routability driven placement algorithms for FPGA synthesis
    Download  csrl.unt.edu
    We present new timing and congestion driven FPGA placement algorithms with minimal runtime overhead. By predicting the post-routing critical edges and estimating congestion accura...
    Yue Zhuo, Hao Li, Qiang Zhou, Yici Cai, Xianlong H...
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