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    ASPDAC
    2005
    ACM
    79views Hardware» more  ASPDAC 2005»
    Simulation acceleration of transaction-level models for SoC with RTL sub-blocks
    13 years 7 months ago
    Simulation acceleration of transaction-level models for SoC with RTL sub-blocks
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    Abstract— This paper presents an optimized channel usage between simulator and accelerator when the simulator models transaction-level SoC while accelerator models RTL sub-blocks...
    Jae-Gon Lee, Woo-Seung Yang, Young-Su Kwon, Young-...
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