ISLPED
2003
ACM
13 years 10 months ago
2003
ACM
A new architectural technique to reduce power dissipation in data caches is proposed. In multimedia applications, a major portion of data cache accesses hit in the same cache set ...
ISLPED
2003
ACM
13 years 10 months ago
2003
ACM
High-performance processors use a large set–associative L1 data cache with multiple ports. As clock speeds and size increase such a cache consumes a significant percentage of t...