ERSA
2009
13 years 2 months ago
2009
- The FPGA (re)configuration is a time-consuming process and a bottleneck in FPGA-based Run-Time Reconfigurable (RTR) systems. In this paper, we present a High Level Synthesis (HLS...
ERSA
2009
13 years 2 months ago
2009
Configuration with Self-configured Data Path (CSDP) is a high speed configuration data loading method for Dynamically Reconfigurable Processors (DRPs). By using a prepared configu...
TPDS
2002
13 years 4 months ago
2002
Abstract--The Gemini interconnect is a dual technology (optical and electrical) interconnection network designed for use in tightlycoupled multicomputer systems. It consists of a c...
TCAD
1998
13 years 4 months ago
1998
—We study the effect of the controller on the testability of sequential circuits composed of controllers and data paths. We show that even when all the loops of the circuit have ...
ISSA
2004
13 years 6 months ago
2004
This paper describes a high data rate 8-bit Crypto Processor based on Advanced Encryption Standard (Rijndael algorithm). Though the algorithm requires 32-bit wide data path but ou...
ASAP
2007
IEEE
13 years 6 months ago
2007
IEEE
In high-level synthesis, as for compilers, an important question is when register assignment should take place. Unlike compilers for which the processor architecture is given, syn...
CAV
2008
Springer
13 years 7 months ago
2008
Springer
This paper proposes a new approach for proving arithmetic correctness of data paths in System-on-Chip modules. It complements existing techniques which are, for reasons of complexi...
VTS
1995
IEEE
13 years 8 months ago
1995
IEEE
In this paper, we propose an entirely new Built-In Self Test scheme for high-level synthesis of data path architectures that makes use of the arithmetic blocks in the data path to...
ICCD
1995
IEEE
13 years 8 months ago
1995
IEEE
We describe thedesign of a high performance asynchronous SCSI Small Computer Systems Interface controller data path and the associated control circuits. The data path is an asyn...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
This paper describes a method to optimize the performance of data paths. It is based on bit-level arithmetic transformations, and is especially suited to optimize large adder stru...