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86
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ISLPED
2003
ACM
111
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ISLPED 2003
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A low-power VLSI architecture for turbo decoding
15 years 8 months ago
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www.ifp.illinois.edu
Presented in this paper is a low-power architecture for turbo decodings of parallel concatenated convolutional codes. The proposed architecture is derived via the concept of block...
Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer
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