VLSID
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper provides a theoretical basis for eliminating or reducing the energy consumption due to transients in a synchronous digital circuit. The transient energy is minimized wh...
VLSID
2003
IEEE
14 years 5 months ago
2003
IEEE
In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number ofconstraints. By intr...
VLSID
2004
IEEE
14 years 5 months ago
2004
IEEE
{A new low-power design method produces CMOS circuits that consume the least dynamic power at the highest speed permitted under the technology constraint. A gate is characterized b...