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ATS
2003
IEEE
151views Hardware» more  ATS 2003»
9 years 3 months ago
BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability
A new technique for synthesizing totally symmetric Boolean functions is presented that achieves complete robust path delay fault testability. We apply BDDs for the synthesis of sy...
Junhao Shi, Görschwin Fey, Rolf Drechsler
DATE
2007
IEEE
83views Hardware» more  DATE 2007»
9 years 4 months ago
High-level test synthesis for delay fault testability
A high-level test synthesis (HLTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embed...
Sying-Jyan Wang, Tung-Hua Yeh
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