Sciweavers

DAC
2005
ACM
14 years 6 months ago
IODINE: a tool to automatically infer dynamic invariants for hardware designs
We describe IODINE, a tool to automatically extract likely design properties using dynamic analysis. A practical bottleneck in the formal verification of hardware designs is the n...
Sudheendra Hangal, Naveen Chandra, Sridhar Narayan...
DAC
2005
ACM
14 years 6 months ago
Locality-conscious workload assignment for array-based computations in MPSOC architectures
While the past research discussed several advantages of multiprocessor-system-on-a-chip (MPSOC) architectures from both area utilization and design verification perspectives over ...
Feihui Li, Mahmut T. Kandemir
DAC
2005
ACM
14 years 6 months ago
Efficient fingerprint-based user authentication for embedded systems
User authentication, which refers to the process of verifying the identity of a user, is becoming an important security requirement in various embedded systems. While conventional...
Pallav Gupta, Srivaths Ravi, Anand Raghunathan, Ni...
DAC
2005
ACM
14 years 6 months ago
Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions
While performance specifications are verified before sign-off for a modern nanometer scale design, extensive application of optical proximity correction substantially alters the l...
Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Denni...
DAC
2005
ACM
14 years 6 months ago
Automatic scenario detection for improved WCET estimation
Modern embedded applications usually have real-time constraints and they are implemented using heterogeneous multiprocessor systems-on-chip. Dimensioning a system requires accurat...
Stefan Valentin Gheorghita, Sander Stuijk, Twan Ba...
DAC
2005
ACM
14 years 6 months ago
Net weighting to reduce repeater counts during placement
We demonstrate how to use placement to ameliorate the predicted repeater explosion problem caused by poor interconnect scaling. We achieve repeater count reduction by dynamically ...
Brent Goplen, Prashant Saxena, Sachin S. Sapatneka...
DAC
2005
ACM
14 years 6 months ago
Incremental exploration of the combined physical and behavioral design space
Achieving design closure is one of the biggest headaches for modern VLSI designers. This problem is exacerbated by high-level design automation tools that ignore increasingly impo...
Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Z...
DAC
2005
ACM
14 years 6 months ago
Minimising buffer requirements of synchronous dataflow graphs with model checking
Signal processing and multimedia applications are often implemented on resource constrained embedded systems. It is therefore important to find implementations that use as little ...
Marc Geilen, Twan Basten, Sander Stuijk
DAC
2005
ACM
14 years 6 months ago
Beyond safety: customized SAT-based model checking
Malay K. Ganai, Aarti Gupta, Pranav Ashar