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DFT
2002
IEEE
128views VLSI» more  DFT 2002»
13 years 10 months ago
Matrix-Based Test Vector Decompression Using an Embedded Processor
This paper describes a new compression/decompression methodology for using an embedded processor to test the other components of a system-on-a-chip (SoC). The deterministic test v...
Kedarnath J. Balakrishnan, Nur A. Touba
DFT
2002
IEEE
121views VLSI» more  DFT 2002»
13 years 10 months ago
Testing Digital Circuits with Constraints
Many digital circuits have constraints on the logic values a set of signal lines can have. In this paper, we present two new techniques for detecting the illegal combinations of l...
Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McC...