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ICCAD
2009
IEEE
151views Hardware» more  ICCAD 2009»
13 years 2 months ago
Timing yield-aware color reassignment and detailed placement perturbation for double patterning lithography
Double patterning lithography (DPL) is a likely resolution enhancement technique for IC production in 32nm and below technology nodes. However, DPL gives rise to two independent, ...
Mohit Gupta, Kwangok Jeong, Andrew B. Kahng
ISQED
2010
IEEE
141views Hardware» more  ISQED 2010»
13 years 11 months ago
Assessing chip-level impact of double patterning lithography
—Double patterning lithography (DPL) provides an attractive alternative or a supplementary method to enable the 32nm and 22nm process nodes, relative to costlier technology optio...
Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topalog...